1. Field of the Invention
The present invention relates to methods for forming conductive vias and electrical contact terminals for substrates, such as semiconductor wafers or other bulk substrates or portions thereof, for use as contact cards, test carriers, package interposers and other substrates, and the like, and the resulting structures and assemblies.
2. State of the Art
Semiconductor wafers and portions thereof are used for substrates for contact cards, test carriers, package substrates, and for other purposes. Typically, the portion of such a substrate has circuits formed on one or both sides for the mounting of one or more semiconductor dice thereon, for making electrical contact to active circuitry of semiconductor dice of a wafer to be tested, and for other purposes. Some portions of substrates, including semiconductor wafers, may have vias extending therethrough filled with conductive material for forming interconnects (commonly known as a through wafer interconnect, or TWI) for connecting circuitry on one side of a portion of the semiconductor wafer to circuitry on the other side thereof, or to external circuitry.
As used herein, a “via” refers to a hole or aperture having conductive material or a conductive member therein which extends through a substrate. The via may be used for electrically connecting a semiconductor device, a component, apparatus, or circuitry on one side of the substrate to a semiconductor device, a component, apparatus, or circuitry on the other side of the substrate. A via may typically be formed in a variety of substrates for a variety of uses, such as interposers for single die packages, interconnects for multi-die packages, and contact probe cards for temporarily connecting semiconductor dice to a test apparatus, for example. For example, a test apparatus is typically configured for temporary simultaneous connection of bond pads of a semiconductor die on a full or partial wafer to the test apparatus. A pattern of conductive vias passing through a substrate employed as a test interposer are designed on one side to match the bond pad patterns of the semiconductor dice on the wafer or portion of a wafer, and on the other side to be connected to the test apparatus.
Where a via is to be formed through a semiconductive material such as silicon, a prior method for constructing a via includes a first or precursor hole being typically formed by a so-called “trepan” process, whereby a very small router or drill is rotated while being moved radially to create the precursor hole. The precursor hole is larger in diameter than the desired completed via to be formed. Following precursor hole formation, an insulation (dielectric) layer is formed in the hole by either forming a thin silicon oxide layer on the hole's surface by exposure to an oxidizing atmosphere or by coating the hole with an insulative polymeric material after oxidizing the hole. When a polymeric insulative material coating is desired, a suitable polymer such as Parylene™ resin may be vapor deposited over the substrate including within each precursor hole while applying a negative pressure, i.e., vacuum, to the opposite end of the hole. Oxidation of the hole surfaces is required because adhesion of polymer to silicon is relatively poor while adhesion to the oxide is much improved. The insulative polymeric material is drawn into each primary hole to fill the hole. The polymer is then cured, and a small diameter via hole is drilled (by percussion drill or laser) or otherwise formed in the hardened insulative polymeric material. The via hole is then filled with a conductive material, typically a metal, metal alloy, or metal-containing material to provide a conductive path between the opposed surfaces of the substrate. The conductive material of the via is insulated from the substrate itself by the insulative polymeric material. In this method of forming vias, dense spacing of vias is difficult to achieve.
Another prior art method for forming vias in a semiconductor substrate is illustrated in drawing FIG. 1A through FIG. 1F. Such a method is also generally illustrated in U.S. Pat. No. 5,166,097 to Tanielian, U.S. Pat. No. 5,063,177 to Geller et al., and U.S. Pat. No. 6,400,172 to Akram et al. Illustrated in drawing FIG. 1A, a silicon wafer 2 is provided with a thin layer 4 of silicon dioxide on at least both major, opposing surfaces. A pattern 6 is then formed on the wafer 2 and a mask layer 8 is formed to prevent etching in non-via areas, as shown in drawing FIG. 1B. In drawing FIG. 1C, etchant has been applied to both major surfaces to form feedthroughs 10 which meet in the middle of the wafer. The wafer 2 is shown with the mask layer 8 removed. A dielectric layer 12 is then formed over the wafer surfaces including the feedthrough side walls, as shown in drawing FIG. 1D. In the next act, illustrated in drawing FIG. 1E, a metal layer 14 is formed over the dielectric layer 12. The wafer is illustrated in drawing FIG. 1F as having a conductive material (shown in broken lines) placed in the feedthroughs 10 to complete the conductive vias 16. It is noted that in order to isolate each via, the metal layer 14 must be configured to cover the feedthrough surfaces only, or be subsequently removed from the outer surfaces of the via and wafer.
As illustrated in U.S. Pat. No. 5,166,097 to Tanielian, in U.S. Pat. No. 5,063,177 to Geller et al., and in U.S. Pat. No. 6,400,172 to Akram et al., the cross-sectional shape of the feedthrough 10 and via 16 is generally that of an hour-glass, with the greatest cross-sectional dimension(s) located at the wafer surfaces. Illustrated in drawing FIG. 2 is an enlarged portion of drawing FIG. 1E. In a preferred embodiment of Tanielian, each half-via 16A, 16B is pyramidal in shape, with a side angle 18 of about 54.7 degrees to the plane of wafer 2. Thus, in this embodiment of Tanielian the minimal ratio of via dimension 30 (of surface 22) to total via depth 32 (substrate thickness) will be in a range of about 0.45 to about 0.52, which is the reciprocal of the via's aspect ratio. As electronic components are becoming increasingly dense, it is necessary to decrease the lateral size or diameter as well as spacing or pitch of TWIs for increased TWI density. To achieve the desired feature densities for TWIs in future electronic components, the aspect ratio of depth 32 to dimension 30 must be considerably larger than about 2.0 for a given substrate thickness.
Illustrated in drawing FIG. 3 is an interposer wherein a method for attaching solder balls/bumps to a via 16 requires that one or both wafer surfaces are mechanically or chemically-mechanically thinned to produce surfaces 34 defining thinned wafer 2. The removal of material from wafer 2 results in exposure of the side surfaces 24 of the via 16, to which a solder bump/ball 20 is wetted and bonded, and exposure of the substrate surface 34. Reflow of a bump/ball 20 results in solder extending about side surfaces 24 of the via 16. Inasmuch as the outer surfaces 22 of the via 16 significantly overlie the substrate surfaces 34, the likelihood of inadvertent contact of solder from ball/bump 20 with the surface 34 increases, and shorting of the via 16 to wafer 2 may occur. It therefore becomes a requirement to provide a passivation layer 36 over surfaces 34 proximate solder/bumps/balls 20, as shown.
In this type of via-to-bump connection, the bumps/balls 20 are susceptible to cracking, particularly at the corners 26 of the via 16. Such cracking leads to break-off of solder from the via 16 due to failure of the via-to-bump adhesion. Without the application of a passivation layer 36 on the surface of the substrate, shorting failures are likely to occur.
In U.S. Pat. No. 6,355,181 to McQuarrie et al., a method is disclosed for making deep trenches having enlarged bottoms or bases. The method comprises applying a mask layer over a substrate, forming a hole in the mask layer and high energy plasma etching anisotropically to a desired depth. A protecting layer is then applied over the hole surfaces and mask layer. Selected portions of the protecting layer are removed from the base surface, and the base is etched to a desired shape.
It is desirable that the aforementioned disadvantages of the prior art be minimized.